? semiconductor components industries, llc, 2000 august, 2000 rev. 7 1 publication order number: mc14541b/d mc14541b programmable timer the mc14541b programmable timer consists of a 16stage binary counter, an integrated oscillator for use with an external capacitor and two resistors, an automatic poweron reset circuit, and output control logic. timing is initialized by turning on power, whereupon the poweron reset is enabled and initializes the counter, within the specified v dd range. with the power already on, an external reset pulse can be applied. upon release of the initial reset command, the oscillator will oscillate with a frequency determined by the external rc network. the 16stage counter divides the oscillator frequency (f osc ) with the n th stage frequency being f osc /2 n . ? available outputs 2 8 , 2 10 , 2 13 or 2 16 ? increments on positive edge clock transitions ? builtin low power rc oscillator ( 2% accuracy over temperature range and 20% supply and 3% over processing at < 10 khz) ? oscillator may be bypassed if external clock is available (apply external clock to pin 3) ? external master reset totally independent of automatic reset operation ? operates as 2 n frequency divider or single transition timer ? q/q select provides output logic level flexibility ? reset (auto or master) disables oscillator during resetting to provide no active power dissipation ? clock conditioning circuit permits operation with very slow clock rise and fall times ? automatic reset initializes all counters on power up ? supply voltage range = 3.0 vdc to 18 vdc with auto reset supply voltage range = disabled (pin 5 = v dd ) supply voltage range = 8.5 vdc to 18 vdc with auto reset supply voltage range = enabled (pin 5 = v ss ) maximum ratings (voltages referenced to v ss ) (note 2.) symbol parameter value unit v dd dc supply voltage range 0.5 to +18.0 v v in , v out input or output voltage range (dc or transient) 0.5 to v dd + 0.5 v i in input current (dc or transient) 10 (per pin) ma i out output current (dc or transient) 45 (per pin) ma p d power dissipation, per package (note 3.) 500 mw t a ambient temperature range 55 to +125 c t stg storage temperature range 65 to +150 c t l lead temperature (8second soldering) 260 c 2. maximum ratings are those values beyond which damage to the device may occur. 3. temperature derating: plastic ap and d/dwo packages: 7.0 mw/ c from 65 c to 125 c http://onsemi.com a = assembly location wl, l = wafer lot yy, y = year ww, w = work week device package shipping ordering information mc14541bcp pdip14 2000/box mc14541bd soic14 55/rail mc14541bdr2 soic14 2500/tape & reel 1. for ordering information on the eiaj version of the soic packages, please contact your local on semiconductor representative. mc14541bdtr2 tssop14 2500/tape & reel mc14541bdt tssop14 96/rail mc14541bf soeiaj14 see note 1. this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid ap- plications of any voltage higher than maximum rated voltages to this highimpedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused out- puts must be left open. mc14541bfel soeiaj14 see note 1. marking diagrams 1 14 pdip14 p suffix case 646 mc14541bcp awlyyww soic14 d suffix case 751a tssop14 dt suffix case 948g 1 14 14541b awlyww 14 541b alyw 1 14 soeiaj14 f suffix case 965 1 14 mc14541b alyw
mc14541b http://onsemi.com 2 pin assignment nc = no connection 11 12 13 14 8 9 10 5 4 3 2 1 7 6 mode nc a b v dd q q/q sel nc r s c tc r tc v ss mr ar ????????????????????????????????? electrical characteristics (voltages referenced to v ss ) v dd 55 c 25 c 125 c characteristic symbol v dd vdc min max min typ (4.) max min max unit output voltage a0o level v in = v dd or 0 v ol 5.0 10 15 e e e 0.05 0.05 0.05 e e e 0 0 0 0.05 0.05 0.05 e e e 0.05 0.05 0.05 vdc a1o level v in = 0 or v dd v oh 5.0 10 15 4.95 9.95 14.95 e e e 4.95 9.95 14.95 5.0 10 15 e e e 4.95 9.95 14.95 e e e vdc input voltage a0o level (v o = 4.5 or 0.5 vdc) (v o = 9.0 or 1.0 vdc) (v o = 13.5 or 1.5 vdc) v il 5.0 10 15 e e e 1.5 3.0 4.0 e e e 2.25 4.50 6.75 1.5 3.0 4.0 e e e 1.5 3.0 4.0 vdc a1o level (v o = 0.5 or 4.5 vdc) (v o = 1.0 or 9.0 vdc) (v o = 1.5 or 13.5 vdc) v ih 5.0 10 15 3.5 7.0 11 e e e 3.5 7.0 11 2.75 5.50 8.25 e e e 3.5 7.0 11 e e e vdc output drive current (v oh = 2.5 vdc) source (v oh = 9.5 vdc) (v oh = 13.5 vdc) i oh 5.0 10 15 7.96 4.19 16.3 e e e 6.42 3.38 13.2 12.83 6.75 26.33 e e e 4.49 2.37 9.24 e e e madc (v ol = 0.4 vdc) sink (v ol = 0.5 vdc) (v ol = 1.5 vdc) i ol 5.0 10 15 1.93 4.96 19.3 e e e 1.56 4.0 15.6 3.12 8.0 31.2 e e e 1.09 2.8 10.9 e e e madc input current i in 15 e 0.1 e 0.00001 0.1 e 1.0 m adc input capacitance (v in = 0) c in e e e e 5.0 7.5 e e pf quiescent current (pin 5 is high) auto reset disabled i dd 5.0 10 15 e e e 5.0 10 20 e e e 0.005 0.010 0.015 5.0 10 20 e e e 150 300 600 m adc auto reset quiescent current (pin 5 is low) i ddr 10 15 e e 250 500 e e 30 82 250 500 e e 1500 2000 m adc supply current (5.) (6.) (dynamic plus quiescent) i d 5.0 10 15 i d = (0.4 m a/khz) f + i dd i d = (0.8 m a/khz) f + i dd i d = (1.2 m a/khz) f + i dd m adc 4. data labelled atypo is not to be used for design purposes but is intended as an indication of the ic's potential performance. 5. the formulas given are for the typical characteristics only at 25 c. 6. when using the on chip oscillator the total supply current (in m adc) becomes: i t = i d + 2 c tc v dd f x 10 3 where i d is in m a, c tc is in pf, v dd in volts dc, and f in khz. (see fig. 3) dissipation during poweron with automatic reset enabled is typically 50 m a @ v dd = 10 vdc.
mc14541b http://onsemi.com 3 ????????????????????????????????? ????????????????????????????????? switching characteristics (7.) (c l = 50 pf, t a = 25 c) characteristic symbol v dd min typ (8.) max unit output rise and fall time t tlh , t thl = (1.5 ns/pf) c l + 25 ns t tlh , t thl = (0.75 ns/pf) c l + 12.5 ns t tlh , t thl = (0.55 ns/pf) c l + 9.5 ns t tlh , t thl 5.0 10 15 e e e 100 50 40 200 100 80 ns propagation delay, clock to q (2 8 output) t plh , t phl = (1.7 ns/pf) c l + 3415 ns t plh , t phl = (0.66 ns/pf) c l + 1217 ns t plh , t phl = (0.5 ns/pf) c l + 875 ns t plh t phl 5.0 10 15 e e e 3.5 1.25 0.9 10.5 3.8 2.9 m s propagation delay, clock to q (2 16 output) t phl , t plh = (1.7 ns/pf) c l + 5915 ns t phl , t plh = (0.66 ns/pf) c l + 3467 ns t phl , t plh = (0.5 ns/pf) c l + 2475 ns t phl t plh 5.0 10 15 e e e 6.0 3.5 2.5 18 10 7.5 m s clock pulse width t wh(cl) 5.0 10 15 900 300 225 300 100 85 e e e ns clock pulse frequency (50% duty cycle) f cl 5.0 10 15 e e e 1.5 4.0 6.0 0.75 2.0 3.0 mhz mr pulse width t wh(r) 5.0 10 15 900 300 225 300 100 85 e e e ns master reset removal time t rem 5.0 10 15 420 200 200 210 100 100 e e e ns 7. the formulas given are for the typical characteristics only at 25 c. 8. data labelled atypo is not to be used for design purposes but is intended as an indication of the ic's potential performance. figure 1. power dissipation test circuit and waveform figure 2. switching time test circuit and waveforms pulse generator v dd c l q r s ar q/q select mode a b mr v ss 20 ns 20 ns 90% 50% 10% 50% duty cycle (r tc and c tc outputs are left open) pulse generator v dd r s ar q/q select mode a b mr v ss c l q 20 ns 90% 50% 20 ns 10% r s q t plh 50% 90% 50% 10% 50% t tlh t thl t phl
mc14541b http://onsemi.com 4 expanded block diagram a12 b13 r tc 1 c tc 2 r s 3 5 auto reset osc reset c 2 8 8-stage counter reset power-on reset 6 master reset 2 10 2 13 2 16 c 8-stage counter reset 1 of 4 mux 10 mode 9 q/q select 8q v dd = pin 14 v ss = pin 7 frequency selection table a b number of counter stages n count 2 n 0 0 13 8192 0 1 10 1024 1 0 8 256 1 1 16 65536 truth table state pin 0 1 auto reset, 5 auto reset operating auto reset disabled master reset, 6 timer operational master reset on q/q ,9 output initially low after reset output initially high after reset mode, 10 single cycle mode recycle mode figure 3. oscillator circuit using rc configuration 3 r s r tc c tc 21 to clock circuit internal reset
mc14541b http://onsemi.com 5 typical rc oscillator characteristics figure 4. rc oscillator stability figure 5. rc oscillator frequency as a function of r tc and c tc 8.0 4.0 0 -4.0 -8.0 -12 -16 125 100 75 50 25 0 -25 -55 t a , ambient temperature ( c) frequency deviation (%) v dd = 15 v 10 v 5.0 v r s = 0, f = 10.15 khz @ v dd = 10 v, t a = 25 c r s = 120 k w , f = 7.8 khz @ v dd = 10 v, t a = 25 c r tc = 56 k w , c = 1000 pf 100 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 1.0 k 10 k 100 k 1.0 m f, oscillator frequency (khz) r tc , resistance (ohms) 0.0001 0.001 0.01 0.1 c, capacitance ( m f) v dd = 10 v f as a function of r tc (c = 1000 pf) (r s 2r tc ) f as a function of c (r tc = 56 k w ) (r s = 120 k w ) operating characteristics with auto reset pin set to a a0o the counter circuit is initialized by turning on power. or with power already on, the counter circuit is reset when the master reset pin is set to a a1o. both types of reset will result in synchronously resetting all counter stages independent of counter state. auto reset pin when set to a a1o provides a low power operation. the rc oscillator as shown in figure 3 will oscillate with a frequency determined by the external rc network i.e., if (1 khz f 100 khz) 2.3 r tc c tc 1 f = and r s 2 r tc where r s 10 k w the time select inputs (a and b) provide a twobit address to output any one of four counter stages (2 8 , 2 10 , 2 13 and 2 16 ). the 2 n counts as shown in the frequency selection table represents the q output of the n th stage of the counter. when a is a1o, 2 16 is selected for both states of b. however, when b is a0o, normal counting is interrupted and the 9th counter stage receives its clock directly from the oscillator (i.e., effectively outputting 2 8 ). the q/q select output control pin provides for a choice of output level. when the counter is in a reset condition and q/q select pin is set to a a0o the q output is a a0o, correspondingly when q/q select pin is set to a a1o the q output is a a1o. when the mode control pin is set to a a1o, the selected count is continually transmitted to the output. but, with mode pin a0o and after a reset condition the r s flipflop (see expanded block diagram) resets, counting commences, and after 2 n1 counts the r s flipflop sets which causes the output to change state. hence, after another 2 n1 counts the output will not change. thus, a master reset pulse must be applied or a change in the mode pin level is required to reset the single cycle operation. digital timer application r tc c tc nc r s ar mr input t mr v dd b a n.c. output v dd mode q/q t + t mr 1 2 3 4 5 6 78 9 10 11 12 13 14 when master reset (mr) receives a positive pulse, the internal counters and latch are reset. the q output goes high and remains high until the selected (via a and b) number of clock pulses are counted, the q output then goes low and remains low until another input pulse is received. this aone shoto is fully retriggerable and as accurate as the input frequency. an external clock can be used (pin 3 is the clock input, pins 1 and 2 are outputs) if additional accuracy is needed. notice that a setup time equal to the desired pulse width output is required immediately following initial power up, during which time q output will be high.
mc14541b http://onsemi.com 6 package dimensions p suffix plastic dip package case 64606 issue m 17 14 8 b a dim min max min max millimeters inches a 0.715 0.770 18.16 18.80 b 0.240 0.260 6.10 6.60 c 0.145 0.185 3.69 4.69 d 0.015 0.021 0.38 0.53 f 0.040 0.070 1.02 1.78 g 0.100 bsc 2.54 bsc h 0.052 0.095 1.32 2.41 j 0.008 0.015 0.20 0.38 k 0.115 0.135 2.92 3.43 l m --- 10 --- 10 n 0.015 0.039 0.38 1.01 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. f hg d k c seating plane n t 14 pl m 0.13 (0.005) l m j 0.290 0.310 7.37 7.87 d suffix plastic soic package case 751a03 issue f notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t t f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019
mc14541b http://onsemi.com 7 package dimensions dt suffix plastic tssop package case 948g01 issue o dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c --- 1.20 --- 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.50 0.60 0.020 0.024 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. s u 0.15 (0.006) t 2x l/2 s u m 0.10 (0.004) v s t l u seating plane 0.10 (0.004) t ??? ??? section nn detail e j j1 k k1 detail e f m w 0.25 (0.010) 8 14 7 1 pin 1 ident. h g a d c b s u 0.15 (0.006) t v 14x ref k n n
mc14541b http://onsemi.com 8 package dimensions f suffix plastic eiaj soic package case 96501 issue o h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 1.42 --- 0.056 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). 0.13 (0.005) m 0.10 (0.004) d z e 1 14 8 7 e a b view p c l detail p m a b c d e e 0.50 m z on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402745 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc14541b/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk
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